Field of Invention
The present invention relates to a chip package and a method of manufacturing a chip package.
Description of Related Art
Electronic products require multiple functions, while the dimension has to remain compact. The semiconductor chip of the electronic products has ever reducing chip size, and the circuit density increases. The manufacturing of semiconductor chip package is therefore more challenging. Wafer level chip package is one type of semiconductor chip packaging. It refers to a production process when all the packaging process and testing are done to the entire wafer, and then it is cut into single chip package.
In a time when the dimension of semiconductor chip shrinks dramatically, circuit density elevates, insulation property of a chip package plays an important role in chip packaging technique. Insulation is also related moisture, temperature or pressure blocking, which has great impact on the reliability of internal circuit of the chip package. This is usually done by forming a passivation layer to cover the circuit after the circuit layout is finished, and the air is blocked out, and then the wafer is cut into independent chip package. However, the side surface of a chip package will not have any passivation layer. Moisture invades from the side surface results in internal circuit oxidation, or in a worse case, the silicon via of the chip package is crushed, leading to incorrect electrical connection.